India Semicon Reporter

30-Jun-06
Module Combines GPS, Bluetooth
by Chitra Giridhar

SiRF Technology India Private Limited has developed a low power integrated GPS-Bluetooth system solution to support short range, wireless inter-device communications. Called SiRFLinkI, this multi-chip module is targeted at applications combining Bluetooth and GPS, including devices that use Bluetooth to communicate location information to devices like mobile phones and PDAs. According to the company, the SiRFLinkI reduces system level costs. SiRF is working on a reference design for a Bluetooth GPS sensor that will enable customers incorporate this module into their products. This reference design is expected to be available in a few months.

The SiRFLinkI is fabricated as an integrated MCM (Multi-Chip-Module) package measuring 6mm x 8mm x1.2mm, and contains RF, baseband and flash memory sections. The baseband section is manufactured using 90nm LP process technology and incorporates an embedded ARM7 processor to control the GPS and Bluetooth sub-systems. The chip interfaces to SRAM, flash memory, SiRF’s GPS/BT RF, and standard serial interfaces like high-speed UARTs and SPI. The MCM chip consumes 26 mA current in the Bluetooth continuous transmit mode, and 28 mA in continuous receive mode.

Since the product is targeted at mobile devices, low-power and small die-size were among the key design requirements. To achieve this, a specialized power-scheme has been implemented between RF and baseband chips, controlled by the ARM processor. It incorporates clock gating at various levels of logic and supports multiple core voltage-domains. These voltage-domains are controlled by on-chip power-switches which can turn-off a domain, when needed, to conserve leakage power.
Since current EDA tools do not fully support these low-power techniques, the India design team used a number of innovative techniques to simulate and verify these power domains, and ensure proper isolation between them. Verification of the power-scheme at the MCM level was another challenge because a number of analog and RF functionalities needed to be modeled to support mixed-mode simulation, and mimic power-down scenarios. While SiRF’s Noida-based team worked on the micro-architecture and design of the baseband chip, the Bangalore team contributed the Bluetooth software and system integration expertise. The baseband section, which represents about 200 man-months of design effort, comprises about 380K gates and embedded-memory.

To ensure a successful baseband design, the SiRF teams first created a test-chip that had all the design and the power-switches controlled externally. Once the working of this was verified, a second production tapeout was done in which the power sequencing was controlled by on-chip logic. The entire chip functionality, including the power-scheme was validated on a FPGA emulation platform prior to the two tape-outs.