India Semicon Reporter
Reporting on the developments and events in the Indian chip design and related software industry.Sunday, July 16, 2006
30-Jun-06
Module Combines GPS, Bluetooth
by Chitra Giridhar
SiRF Technology India Private Limited has developed a low power integrated GPS-Bluetooth system solution to support short range, wireless inter-device communications. Called SiRFLinkI, this multi-chip module is targeted at applications combining Bluetooth and GPS, including devices that use Bluetooth to communicate location information to devices like mobile phones and PDAs. According to the company, the SiRFLinkI reduces system level costs. SiRF is working on a reference design for a Bluetooth GPS sensor that will enable customers incorporate this module into their products. This reference design is expected to be available in a few months.
The SiRFLinkI is fabricated as an integrated MCM (Multi-Chip-Module) package measuring 6mm x 8mm x1.2mm, and contains RF, baseband and flash memory sections. The baseband section is manufactured using 90nm LP process technology and incorporates an embedded ARM7 processor to control the GPS and Bluetooth sub-systems. The chip interfaces to SRAM, flash memory, SiRF’s GPS/BT RF, and standard serial interfaces like high-speed UARTs and SPI. The MCM chip consumes 26 mA current in the Bluetooth continuous transmit mode, and 28 mA in continuous receive mode.
Since the product is targeted at mobile devices, low-power and small die-size were among the key design requirements. To achieve this, a specialized power-scheme has been implemented between RF and baseband chips, controlled by the ARM processor. It incorporates clock gating at various levels of logic and supports multiple core voltage-domains. These voltage-domains are controlled by on-chip power-switches which can turn-off a domain, when needed, to conserve leakage power.
Since current EDA tools do not fully support these low-power techniques, the India design team used a number of innovative techniques to simulate and verify these power domains, and ensure proper isolation between them. Verification of the power-scheme at the MCM level was another challenge because a number of analog and RF functionalities needed to be modeled to support mixed-mode simulation, and mimic power-down scenarios. While SiRF’s Noida-based team worked on the micro-architecture and design of the baseband chip, the Bangalore team contributed the Bluetooth software and system integration expertise. The baseband section, which represents about 200 man-months of design effort, comprises about 380K gates and embedded-memory.
To ensure a successful baseband design, the SiRF teams first created a test-chip that had all the design and the power-switches controlled externally. Once the working of this was verified, a second production tapeout was done in which the power sequencing was controlled by on-chip logic. The entire chip functionality, including the power-scheme was validated on a FPGA emulation platform prior to the two tape-outs.
Module Combines GPS, Bluetooth
by Chitra Giridhar
SiRF Technology India Private Limited has developed a low power integrated GPS-Bluetooth system solution to support short range, wireless inter-device communications. Called SiRFLinkI, this multi-chip module is targeted at applications combining Bluetooth and GPS, including devices that use Bluetooth to communicate location information to devices like mobile phones and PDAs. According to the company, the SiRFLinkI reduces system level costs. SiRF is working on a reference design for a Bluetooth GPS sensor that will enable customers incorporate this module into their products. This reference design is expected to be available in a few months.
The SiRFLinkI is fabricated as an integrated MCM (Multi-Chip-Module) package measuring 6mm x 8mm x1.2mm, and contains RF, baseband and flash memory sections. The baseband section is manufactured using 90nm LP process technology and incorporates an embedded ARM7 processor to control the GPS and Bluetooth sub-systems. The chip interfaces to SRAM, flash memory, SiRF’s GPS/BT RF, and standard serial interfaces like high-speed UARTs and SPI. The MCM chip consumes 26 mA current in the Bluetooth continuous transmit mode, and 28 mA in continuous receive mode.
Since the product is targeted at mobile devices, low-power and small die-size were among the key design requirements. To achieve this, a specialized power-scheme has been implemented between RF and baseband chips, controlled by the ARM processor. It incorporates clock gating at various levels of logic and supports multiple core voltage-domains. These voltage-domains are controlled by on-chip power-switches which can turn-off a domain, when needed, to conserve leakage power.
Since current EDA tools do not fully support these low-power techniques, the India design team used a number of innovative techniques to simulate and verify these power domains, and ensure proper isolation between them. Verification of the power-scheme at the MCM level was another challenge because a number of analog and RF functionalities needed to be modeled to support mixed-mode simulation, and mimic power-down scenarios. While SiRF’s Noida-based team worked on the micro-architecture and design of the baseband chip, the Bangalore team contributed the Bluetooth software and system integration expertise. The baseband section, which represents about 200 man-months of design effort, comprises about 380K gates and embedded-memory.
To ensure a successful baseband design, the SiRF teams first created a test-chip that had all the design and the power-switches controlled externally. Once the working of this was verified, a second production tapeout was done in which the power sequencing was controlled by on-chip logic. The entire chip functionality, including the power-scheme was validated on a FPGA emulation platform prior to the two tape-outs.
Monday, April 10, 2006
21-Feb-06
India Semicon Industry Should Tap Japanese MNCs
by Chitra Giridhar
“India should take proactive approach to woo Japanese MNCs in the semiconductor space,” advises Dhanukonda Rama, Director, SoCrates Software India Pvt Ltd (a Toshiba Group Company). He believes that many Japanese companies are interested in setting up base in India but are deterred by the cultural differences, perceived lack of manufacturing abilities and quality consciousness. As evidence, he points to the recent burst of investment from many MNCs in India--but none of them are from Japan. Among the companies that recently announced is Tessolve Services, which provides solutions for test development, failure analysis and reliability tests for semi-conductor companies. Tessolve plans to set up a testing, assembling, packaging and prototyping facility in South India. The company plans to invest $200 million over four years. Swedish giant Ericsson also announced its plans to invest $100 million in India.
Earlier SemIndia, a semiconductor manufacturing company set up by a consortium of non resident Indians, finalized plans to set up chip manufacturing plant in Andhra Pradesh. SemIndia will spend $1 billion in the first phase of constructing the $3-billion plant, which includes testing and assembly.
http://www.soc-soft.com
India Semicon Industry Should Tap Japanese MNCs
by Chitra Giridhar
“India should take proactive approach to woo Japanese MNCs in the semiconductor space,” advises Dhanukonda Rama, Director, SoCrates Software India Pvt Ltd (a Toshiba Group Company). He believes that many Japanese companies are interested in setting up base in India but are deterred by the cultural differences, perceived lack of manufacturing abilities and quality consciousness. As evidence, he points to the recent burst of investment from many MNCs in India--but none of them are from Japan. Among the companies that recently announced is Tessolve Services, which provides solutions for test development, failure analysis and reliability tests for semi-conductor companies. Tessolve plans to set up a testing, assembling, packaging and prototyping facility in South India. The company plans to invest $200 million over four years. Swedish giant Ericsson also announced its plans to invest $100 million in India.
Earlier SemIndia, a semiconductor manufacturing company set up by a consortium of non resident Indians, finalized plans to set up chip manufacturing plant in Andhra Pradesh. SemIndia will spend $1 billion in the first phase of constructing the $3-billion plant, which includes testing and assembly.
http://www.soc-soft.com
Monday, February 27, 2006
14 December 05
Cadence Steps Up India Operations
by Chitra Giridhar
Cadence Design Systems (India) has disclosed plans to augment its staff from 700 to over 1,000 in the next few months. Speaking on the sidelines of an event to launch the Cadence RF Design Methodology Kit in Bangalore, Himanshu Singh, Executive Director for India and SAARC said some of this expansion is been driven by the growth in the Indian customers using Cadence tools. Cadence has two design and development centers in India, with its Noida (near Delhi) facility being the largest outside of the US.
It is estimated that more than 150 companies in the country are actively using a variety of Cadence tools. The software is also widely used in education sector, with many universities incorporating it into their engineering curriculum. To promote the use of EDA amongst the student community, the company has announced an EDA design contest for India and the SAARC region. According to Cadence, the contest will provide young designers an opportunity to showcase their best analog mixed signal/digital design projects to be judged by a panel of eminent experts from the industry.
www.cadence.com
18 November 2005
Motorola to expand presence in India, plans to assemble handsets in India
Chitra Giridhar
Motorola’s C115 handsets will now have a "Made in India" label said the company officials. "India is all about opportunity -- and today's announcements make it clear that Motorola is here to be a major player," said Allen Burnes, corporate vice president for the High Growth Markets operation within Motorola's Mobile Devices business.
"We're doing our part to leverage and create opportunities -- both for India and for Motorola. From our higher-end 'must haves' such as the new Motorola L6 candy bar and our best-selling RAZR clamshell, to our hugely popular C115, Motorola is helping connect the unconnected. This creates new and exciting opportunities -- and the potential for many new firsts -- for India's consumers."
The company expects the first Motorola C115 handsets assembled in India will be available by mid-December this year. Assembly in India is the first step in a multi-phase manufacturing strategy being deployed by Motorola in India.
The company also announced that it has selected India as the first market to launch its new ultra-sleek Motorola L6 mobile handset.
www.motorola.com
16 November 05
Tensilica enters design centre agreement with Tata Elxsi
by Chitra Giridhar
Tensilica, Inc., supplier of configurable and extensible microprocessor cores, has entered into an agreement with Bangalore-based Tata Elxsi Ltd., an embedded product design services company.
Based on the agreement, Tata Elxsi will become a recommended design center for Tensilica and Tata Elxsi's engineers will be fully trained on Tensilica's Xtensa(R) processor design technology.
"Having met Tensilica's high standards for an authorized design center, Tata Elxsi will now play a significant role in ensuring the broad and rapid proliferation of Xtensa cores in embedded applications," said Larry Przywara, director of strategic alliances for Tensilica.
As part of the "Tensilica Xtensions Network," design center members have been authorized to assist Xtensa licensees with the configuration, implementation and evaluation of system-on-chip (SoC) designs.
"The partnership reflects our intent to support product development services with technologies that enable significant performance benefits and faster time-to-market across various verticals," stated Mr. Madhukar Dev, CEO, Tata Elxsi.
The Xtensa configurable and extensible microprocessor architecture provides an integrated hardware and software development environment with thousands of configuration options and an unlimited range of customer-specific extensions. The environment enables designers to carefully tune the processor for their particular application.
www.tensilica.com
www.tataelxsi.com
12 November 05
Wipro’s Chairman receives IEE’s Faraday Award
by Chitra Giridhar
Azim Premji, Chairman of Wipro Ltd, was awarded the Faraday Medal by the Institution of Electrical Engineers (IEE)--the largest professional engineering society in Europe. He is the first Indian to receive this prestigious award.
The medal was awarded to him in recognition of his outstanding business leadership and contributions to elementary education in India. Sir Robin Saxby, Chairman of the UK-based ARM Technologies, a recipient of this award in 2002, presented the medal to Premji.
"The medal is actually a recognition of the untiring contribution made by the software engineers at Wipro and the Indian software community in general towards global technology," Premji said in his acceptance speech.
The Faraday Medal is a bronze medal established in 1922, and is awarded not more than once a year, either for notable scientific or industrial achievement in electrical engineering or for conspicuous service rendered to the advancement of electrical science, without restriction as regards nationality, country of residence or membership of the IEE.
Previous recipients of the Faraday Medal include Oliver Heaviside, the first person to receive the medal in 1922; Professor C.K. Kao, the “father” of fibre optic communications in 1989; and Professor P.M. Grant in recognition of his outstanding work on signal processing in 2004.
www.wipro.com
07 November 05
Synplicity to expand Bangalore centre
by Chitra Giridhar
US-based Synplicity, supplier of software for the design and verification of semiconductors, has expressed interest in increasing the scope of work and personnel at its R&D center in Bangalore. Bangalore centre does both development as well as support work. Recently, the five-year old development center has moved to take on autonomous development projects for the company.
Gary Meyers, president and CEO of Synplicity said that the company is doing more development in India. He said that nearly one-fifth of the company's overall R&D team was located in India, making Bangalore centre the second largest. "We have 40 employees at present, and we plan to increase this to 60 by the end of next year."
Synplicity provides tools for electronic design automation (EDA) designers who work on Field Programmable Gate Array (FPGA) synthesis, structured/platform ASIC synthesis and cell-based ASIC products. The company has done custom product development through joint R&D efforts for Altera and Xilinx to provide them exclusive tools.
The company's customer base spans organizations like Cisco Systems, HP, nVIDIA, Texas Instruments, Lockheed Martin, ST Microelectronics and Alcatel. Synplicity's competitors include Mentor Graphics and Synopsys.
www.synplicity.com
07 November 05
Indian government pursues Fab City project
by Chitra Giridhar
The Indian government is planning to build a semiconductor fabrication facility. The central government is surveying regional governments about water and electric facilities, and the concessions they could extend for the proposed project. The project is being supported by Minister for Communications and Information Technology Dayanidhi Maran, who is reportedly keen on having at least one major fabrication facility in the country. The blue print for the fab city will be ready in December.
“We are looking for about 1,500 acres of land for the project, of which 200 acres will be for the foundry and fab facility," says Madhavan Nambiar, Additional Secretary, Ministry of Information and Communication Technology. "A fab plant in India is the need of the hour," said India Semiconductor Association, Vice-Chairman, Anand AnandKumar.
The government is also contacting Taiwan’s Industrial Technology Research Institute (ITRI) to learn about promoting hardware growth in India. “An Indian team will visit ITRI in January,” Nambiar said.
www.isaonline.org
29 October 05
Huge potential and opportunity for semiconductor start-ups in India
by Chitra Giridhar
Availability of quality talent, thriving and collaborative ecosystem, key market drivers (healthy domestic and global market), labor costs are the factors conducive for an environment that fosters start-ups. This was the message at the conference, “Accelerating Technology Incubation in Semiconductor Space”, organized by the India Semiconductor Association (ISA).
S Uma Mahesh, ISA, said, “Semiconductor funding is different from funding a software-based start-up. Incubators need to play the role of a guide right through the initial stages. Incubation need not only be for the person starting a new company, it can also be for an established business with a great technology idea.”
“India Semiconductor Industry has a potential to grow to $40 billion by 2007. The industry can have a huge impact on the GDP of the country,” says Dr Anand Anandkumar, Vice Chairman, ISA. “I hope to see more entrepreneurs approaching the ISA and STPI for help in setting up businesses,” says Poornima Shenoy, President, ISA.
www.isaonline.org
12 October 05
ARM to increase headcount in India
by Chitra Giridhar
U.K.-based ARM is planning to expand its development centre and increase headcount in India. “We intend to do a lot more design activity in India,” said Sir Robin Saxby, Chairman, ARM Embedded Technologies Pvt. Ltd. The company currently has 120 team members in the country, and about 25 contractors according to Saxby. Four Indian companies, Wipro Ltd, HCL Technologies, Mindtree Consulting and Sasken Communications run ARM-approved design centers.
“We have grown ahead of our plans for the country in technology and commercial terms and we only expect to grow here,” said Saxby. He also commented on India’s advantage over China in the area of product patents--which is being driven by the nation’s growing market and design strengths.
www.arm.com
05 October 05
Simulation tools increase designer productivity
by Chitra Giridhar
Model-based design (MBD) is widely used by electronics, semiconductor and wireless industries to design complicated control systems in aerospace, automotive and industrial applications. It enables designers to mathematically and visually model the expected behavior of a product, design software, and simulate its behavior. Not surprisingly, MBD has become well entrenched in India.
According to Mathworks, a US-based company that makes tools for simulation and model-based design, there are more than 5,000 active users of its Matlab and Simulink tools in India. These users include GE India Technology Center, HAL (Hindustan Aeronautics), Tata Motors, TCS, Wipro Technologies, Aeronautical Development Agency (ADA), and IIT Delhi.
Arif Ali Saiyed, Software Engineer, Honeywell Technology Solution Lab, says, “Honeywell uses Matlab Simulink for designing lighting control systems. This software eliminates many manual processes--saving time and development costs.” He feels that no other competing products offer these benefits.
Ritwik Majumder, Senior System Engineer, Siemens Information Systems Ltd. concurs that MBD tools reduce cost and effort by enabling designers visualize results and tune designs. Siemens designs automotive engine management systems and power trains. The company uses Mathlab Simulink models for the control algorithms.
However, Arif feels that more features could be added in the Mathlab. He says that the state-flow coder needs to be enhanced to support Honeywell’s business needs--and product support can be enhanced.
www.mathworks.com
www.htc.honeywell.com
www.siemens.com
04 October 05
Midas selects Infineon chips for fixed wireless product
Targets telcos with broadband VOIP access device
by Chitra Giridhar
Chennai-based Midas Communication Technologies, provider of network access solutions, has selected Infineon Technology’s customized system-on-chip (SoC) solution, INCA-IP, for its broadband corDECT-based fixed wireless access indoor unit. The INCA-IP is a cost-optimized solution for VoIP terminals that offers advanced features such as voice packet prioritization, integrated voice codecs with conferencing functionality, echo-cancellation, and an integrated 3 port Ethernet switch.
“When selecting a SoC solution for the controller in the corDECT indoor unit we looked for one that would facilitate complete host controller functionality, with the smallest footprint and power consumption,” said Rene Abraham, CTO, Midas. The company’s new products based on this SoC will support data rates up to 256 Kbps--more than two and a half times higher than competing platforms.
Midas' current activities in access technologies include "BroadbandcorDECT" a fixed wireless access solution, to cater to the 'last-mile' requirements of wireless service providers, and "Broadband DIAS", an integrated fiber in local loop platform for telephony and broadband services.
www.midascomm.com
www.infineon.com
04 October 05
Indian tool company partners to bring new software tools
by Chitra Giridhar
Bangalore-based scientific and engineering software products and solutions provider, Cranes software has tied-up with Mapusoft Technologies (MT), to bring OSChanger and OS Abstractor software tools to the Indian embedded industry.
While OS Changer allows developers to easily port existing code base to another RTOS and continue code development using the familiar API (application programming interface), OS Abstractor allows developers to write code that can be easily adapted to multiple RTOS’s. OSChanger reduces testing efforts and related risks, and ensures a smooth and successful RTOS transition.
By providing wrapper-less RTOS abstraction APIs, Unix-style device I/O APIs, and a set of core ANSI APIs, OSChanger provides an off-the-shelf RTOS integration solution that enables customers to re-use existing code base and port open source and/or other solutions to theirs easily., all of which are accomplished using a familiar API to get the job done much faster.
OS Abstractor is available for Linux, iTRON, Nucleus PLUS(r), ThreadX(r), Precise/MQX(tm) and other RTOS’s OS Abstractor consists of a set of RTOS-equivalent functions and Unix-style device I/O functions that are highly optimized for specific RTOS’s. Many of the kernel-equivalent RTOS functions are directly mapped to the underlying API and data structures, allowing the translations to occur during compile time, so that run-time performance can be kept intact. The interface to the underlying target RTOS is isolated in a single module to allow easy extension of support to a proprietary or preferred commercial RTOS.
www.cranessoftware.com
www.mapusoft.com
04 October 2005
Mistral announces next gen IP media processing platforms
by Chitra Giridhar
Indian embedded software and hardware development firm, Mistral Solutions, has announced IP media processing platforms, CG 6565 and CG 6060, to deliver increased IP packet processing capability for IVR, fax, conferencing, VoIP and 3G video. The CG 6565 is a high-performance board designed for processing-intensive applications like IP media servers, VoIP gateways, video gateways and media servers. The CG 6060 is a medium-powered board appropriate for a broad range of applications, from high-density trunking with up to 16 E1/T1s, to IVR, fax, conferencing, and MRCP speech. Both the CG 6565 and CG 6060 are available in PCI and compact PCI format.
This new technology is supported by NMS’ development environment, natural access and support MRCP speech servers from all the popular speech vendors through NMS’ Uni
versal Speech Access API (application programming interface). NMS Communications is a mobile application and infrastructure solutions provider.
www.mistralsoftware.com
11 July 2005
eInfoChips targets burgeoning demand for DSPs
Enhances focus on TI’s platforms, adds design staff
by Chitra Giridhar
eInfochips, a chip and systems design services firm with operations in Ahmedabad and Pune, India is collaborating with Texas Instruments (TI) to develop DSP-based reference applications like IP set-top boxes and digital video recorders for OEM designs.
To tap the growing demand for DSP-based designs, eInfochips is ramping up the strength of its engineering team from the current 50 to more than 100 in the next few months. Simultaneously, the company plans to expand its reach in Europe and Asia-Pacific to service TI customers.
The company has already developed several reference designs on TI C6x and DM64x platform, including a KVM/IP (Keyboard, Video, Mouse over IP) for remote server management, a rapid development platform for multimedia applications like DVRs and video conferencing systems, and a networked video application.
eInfochips also offers system integration services to customers developing products on the TI TMS320C6000 DSP platforms, and the TMS320DM64x DSP-based digital media processors. These services include algorithm design and development, selection of DSP processor best suited for the application, processor specific optimization of software, porting and preparing board support packages for RTOS on DSP, and developing board level systems and firmware solutions on DSP.
www.einfochips.com
www.ti.com
05 July 05
Open-Silicon sets up first Design Center Unit in Bangalore
by Chitra Giridhar
Open-Silicon Inc, a fables ASIC company has set up their first design centre unit (DCU) in Bangalore. Built with a world-class silicon engineering and execution capability,Open-Silicon has taped-out 15 chips in the first year of operation. A DCU uses dynamic staffing of technology experts who are specialized in particular silicon-engineering areas. This ensures their customers get a repeatable, predictable and reliable design process for custom ASIC development.
Dr. Naveed Sherwani, President & CEO, Open-Silicon said, "India has been, and continues to be, a very critical part of our growth strategy. The high quality of engineering talent has allowed us to build a multi-function site capable of managing all aspects of silicon engineering. This, combined with the support we have received from the government and industry will allow us to continue to scale to greater heights."
Co-founder and VP Engineering, Dr. Satya Gupta said, "The quality of experienced engineering, university programs that ensure continuous growth of VLSI talent, and local support from ASIC partners for chip design activity make India the ideal place for our silicon engineering efforts. We hope to add our next DCU, double our present work force in 2006 and tape-out 20-25 chips."
www.open-silicon.com
05 July 05
Tessolve sets up product test facility in Bangalore
First to offer services in Asia-Pac region
by Chitra Giridhar
Tessolve Inc. is setting up a facility to provide product engineering (RF, Digital & Mixed Signal) services to global and local customers. This test lab is located in Bangalore’s Semicon Park, a one-stop post-design and post-fab, service facility for semiconductor companies.
The $10 million engineering and testing facility is spread over 50,000 sq. ft. and has an extensive array of advanced testing equipment. Currently the Indian operations employs more than 50 testing professionals with experience in wafer sort, final test development (RF, Digital and Mixed signal) and device characterization. P Raja Manickam, Founder & CEO, Tessolve, says, “This facility, which is equipped to provide world class test development, failure analysis and reliability testing will allow semiconductor companies to go beyond GDS II, for the first time in India.”
According to V Veerappan, vice-president of operations at Tessolve, the company will serve organizations like Texas Instruments, STM, Agere, Broadcom, Insilica, Sitar, SCL and Beceem Communications. Speaking at the inauguration of the facility, Johny Mathew, CEO of Semicon Park said, “The Indian semiconductor industry has been primarily in the design and related services. However, being limited only to being a design services hub has a strategic disadvantage--as it constrains the total value that we can provide. India needs to offer a much more comprehensive ecosystem--which is being realized now.” Concurrs Rajendra Kumar Khare, Chairman of Indian Semiconductor Association (ISA), “The setting up of full-fledged testing facility marks a move towards creating a complete ecosystem for the Indian semiconductor industry.”
www.tessolve.com
www.isaonline.org
30 June 05
Philips expands its India design center
Focus on next generation consumer chips, reusable IP blocks
by Chitra Giridhar
Philips Semiconductors has announced that its Bangalore design center would be working on the next generation consumer platform chip design. Chief Technology Officer Rene Penning de Vries said, "Our center is now fully staffed, and we are embarking on designs in 65 and 90nm. The next generation consumer platform chip will enable new applications such as HD motion based enhancements and 3D TV. It will be the biggest chip we have ever designed in this company and will consist of multiple MIPS and Trimedia (DSP) processors.” The Trimedia processor is a Philips proprietary DSP based on VLIW architecture and allows for video signal processing.
Penning de Vries confirmed that the development of the chip will involve collaborative efforts across multiple sites in Europe and US. “Our Bangalore team will be integrating the whole chip. We will also be working with Philips Research in Bangalore and the Netherlands.”
In addition to working on the new chip, the Bangalore center will also focus on reusable IP. “Our team here will become responsible for a large part of our reuse portfolio. We are enhancing our IP development, and expanding our work in the areas of connectivity peripherals. Our competencies in the reuse IP portfolio include connectivity blocks, wired and wireless, intra and inter chip; SoC, peripherals and drivers. These are being leveraged to provide SoC integrators with ready to use subsystems, which can be easily plugged to build complex SoCs,” Penning de Vries said.
Philips Semiconductor has more than 500 people and working on latest technologies in SoC and embedded software. To support its development efforts, the company plans to hire more many engineers over the next three years.
www.semiconductors.philips.com
24 June 05
Indian startup provides offshore engineering support services
Targets semiconductor, instrumentation and medical electronics sectors
by Chitra Giridhar
Vignani Technologies, a product engineering services company, has commenced operations in Bangalore. Targeting the international semiconductor, instrumentation and medical electronics industries, Vignani offers engineering support services like PCB test and design, modeling, engineering change implementation, embedded solutions and value engineering services.
Explains Tom Rohrs, Chairman, Vignani Technologies, “India is emerging as an important destination for Engineering services. Large multinationals continually allocate scarce engineering manpower to their next generation products, leaving critical revenue producing products under-resourced. Vignani will step in and fill this void.” Funded by a combination of angel and venture capital, Vignani is aiming to hire 750 to 1000 engineers over the next three years. The facility in Bangalore will focus on delivering the services to customers in US, Europe and Japan.
www.vignani.com
16 June 2005
einfochips to double headcount
Plans to tap markets in Europe and Asia
by Chitra Giridhar
eInfochips, a chip & systems design services firm based in Santa Clara, USA and Ahmedabad, India, plans to double the headcount at its research and development centers this year and tap new markets. The company plans to increase the headcount at its design centers from the current strength of 270 engineers to over 550 engineers. eInfochips has a state-of-the-art 40000 sq. ft. design center employing over 250 design engineers in Ahmedabad.
“We plan to open our first office in Europe either in UK or Germany, while for Asia-Pacific region, Japan is under active consideration,” says Pratul Shroff, President & CEO, eInfochips.
“The demand for technology services is large and we see ourselves growing rapidly. The market potential for outsourced engineering services is estimated to lie between $ 7 to $12 billion and around 20% of the value is being outsourced to third party vendors in countries like India, Taiwan and China which highlights significant untapped potential. We will recruit a large number of engineers this year and offer them an opportunity to work on cutting edge technology like GPS navigation, digital MP3 players, video-on-demand, UWB (wireless) and SAN (storage area networking),’’ adds Shroff.
“eInfochips has been founded with a singular vision: to build an enduring, world-class technology services organization to serve customers globally. People are the key in realizing this vision. We are strongly focused on helping each individual maximize his potential,” adds Shroff.
eInfochips has specialization in design and verification of Application Specific Integrated Chips (ASIC) and provides embedded systems solutions, application software and IP cores to world’s best-known technology companies such as Samsung, Texas Instruments, Cadence, Rambus, Qlogic, Tensilica, Cypress Semiconductor, Agere, Navionics, Sun Microsystems and NetEffect.
eInfochips has recently opened up two more sales offices in US in Boston and Austin, and one sales office in India at Banglore. Last year it set up a new development and design facility in Pune. The Pune Center is executing offshore projects for global blue chip technology companies like QLogic and Tensilica.
eInfochips has proven competencies in the complete product development life cycle, right from Hardware Design, Firmware Development, Multimedia Codecs, Communication stacks, and application development. ‘DSPKarma™’ is the suite of DSP Services that includes DSP Hardware, Software and System Integration. eInfochips has also recently introduced ‘ChipMaestro’- the industry’s first suite of solutions and services, as a single source of offshore expertise in the design, development and verification of SoCs, ASICs or FPGAs for the communications and computer peripheral markets.
www.einfochips.com
06 June 05
SiNett simplifies integration of wired, wireless LANs
Reference platform for unified networks bundles management software for rapid prototyping
by Chitra Giridhar
SiNett Corp., a developer of silicon for networking apps is partnering with NextHop Technologies Inc., network software solutions provider to support the design of enterprise-class integrated wireless and wired network access products. According to Shrikant Sathe, co-founder and vice president of marketing at SiNett, “Our technology coupled with NextHop's WLAN controller software will provide equipment manufacturers with a flexible solution for building and managing unified wireless and wired network infrastructures.”
The partnership envisages tight coupling of SiNett's switch processor and NextHop's wireless LAN controller software (WCS) to meet enterprise requirements for L2/L3 switching and wireless LAN (WLAN) management. These include the provisioning of seamless mobility, enhanced security, quality of service (QoS) and advanced traffic management. OEMs and ODMs using the solution can deploy the switch process and controller software combination in equipment designed for any layer in the network.
A demo version of NextHop's software will be included with SiNett's OneEdge-based OneRunner platform, a reference design for developing secure WLAN and unified access (UA) switches and WLAN appliances. OneRunner is designed to support different access point architectures such as ultra-thin and thin access points. SiNett’s SN5024 UA switch processor incorporates 24 Fast Ethernet (FE) and 4 Gigabit Ethernet (GE) interfaces, and can be used in fixed configuration or stackable Unified Access switches. The NextHop demo software provides advanced security, authentication, mobility, QoS and centralized management for WLAN (802.11) access points.
www.sinett.com
www.nexthop.com
03 June 05
HCL, NEC form joint venture company
New entity to deliver offshore-based services to Japan clients
by Chitra Giridhar
NEC Corp. has entered into a joint venture with India-based HCL Technologies Limited (HCL) for offshore software engineering solutions in embedded software, hardware design, network & security, R&D, high performance computing, and mobile technology to NEC, its subsidiaries and their clients, in Japan and globally. NEC Corp. and its subsidiary, NEC System Technologies Ltd, will have a 51% stake in the joint venture, while remaining will be held by HCL. The new company is expected to achieve revenues of about US $25 million in three years.
The joint venture will be based out of Noida, India. HCL will provide the CEO and CTO, along with some key technical people to initiate the JV. This alliance is a part of NEC's strategic intent to harness Indian IT prowess and leverage its IT eco-system advantages to provide greater value of IT products and services to its subsidiaries and their clients globally. Hiroshi Oka, Associate Senior Vice President, NEC System Technologies Ltd. said, "I have a lot of expectations from the JV and HCL in areas such as embedded software, network and security products, hardware design and related tools."
www.hcltech.com
www.nec.com
20 May 05
Toolkit solves post-layout data organization
Interfaces to existing tools, and speeds development of custom solutions
by Chitra Giridhar
Bangalore-based SoftJin Infotech Pvt. Ltd. has developed an EDA toolkit that addresses the challenges of geometric data-organization at the post layout stage of the sub-90 nm IC manufacturing process. According to the company, Nirmaan, is a performance tuned and customized toolkit that obviates the need for EDA tool developers to develop their own code for geometrical operations. Nachiket Urdhwareshe, CEO, Softjin says, “Our goal is to support the development of customized DFM/DFY tools with our building blocks and services".
Nirmaan provides APIs for post-layout EDA tool developers to enable them integrate the toolkit into their own solutions. Nirmaan stores and represents geometric data in multiple levels of organizations (including structural, spatial and basic geometry levels), and allows mixing and matching of different types of organizations at different levels. The flexibility of data organization makes the toolkit highly efficient for performing the geometrical operations required in post-layout tools. The data is stored in compressed form and is decompressed on-the-fly. API’s are available for the tool developers to plug-in customized data models.
The built-in geometrical operations in Nirmaan include boolean, sizing, islanding, tiling/binning and window querying. These operations work on the in-memory data organization, and can be performed at polygon, cell, island, window, layer, block and full-chip levels. To boost performance, the toolkit’s data-organization and operations support multi-threading and distributed computing. The product interfaces with other applications through standard industry layout data formats and databases like GDSII, OASIS, LEF/DEF and OpenAccess.
Nirmaan can be used to accelerate product development for companies developing new post layout tools. Also, companies with existing post layout EDA products can adopt the product to improve the performance and scalability of their current solutions. The toolkit is licensed as object code, and can be included and sold as part of post-layout tools. Licenses start at $150,000. Nirmaan is currently available to select beta sites, and will be in production release in Q3-2005. The toolkit will be demonstrated at the Design Automation Conference in Anaheim, June 13-16 [SoftJin booth # 1956].
www.softjin.com
17 May 05
“Assertion-based design verification is a pre-emptive approach”
by Chitra Giridhar
San Jose-based Atrenta Inc. has developed a chip verification solution, 1Team:Verify, that enables IC designers detect and prevent hard-to-find bugs earlier in design process. The solution can detect many "corner-case" bugs that traditional simulation-based verification methods can miss. Examples include errors involving clock domain crossings (CDCs), finite state machines (FSMs), handshake mechanisms and bus structures. Verify can generate and validate a large number of assertions (over 10,000 assertions for a 500,000-gate design on average) without any user intervention.
Verify allows RTL designers to carry out many ABV checks themselves, thus saving time and cost. In addition to its fully automatic checking, Verify also allows more experienced users to write their own assertions using other assertion languages. Verify supports the open verification library (OVL)--an Accellera-standard library of 31 predefined assertions from which users can choose. Extensions to OVL are also supported for users who want to define new assertions using the OVL paradigm. PSL (Property Description Language) and SVA (System Verilog Assertions) are also available as Verify options.
Mani Narayan, Product Marketing Director for Atrenta talks to Chitra Giridhar about Verify.
CG: How long did it take you to develop the Verify solution?
MN: Verify is built on some of the key technologies that form the foundation of Atrenta’s SpyGlass product [introduced in January 2001]. Additional technology was developed to provide in-depth functional verification, and seek out hard to find functional problems. The new technology for Verify took more than 2 years to develop, and the product represents more than 40,000 man hours of work. More than 90% of the development was done at our Noida, India facility.
CG: What were the main challenges you encountered in developing the solution?
MN: First a historical perspective. Formal verification technology has been around for 10 years and all assertion based verification products developed using this technology have been difficult for RTL designers to use. The need to learn a language like PSL and getting familiar with the formal terminology have all been barriers to adoption. The process of understanding user needs and translating them into features that could be mapped into technologies was one of the key challenges.
CG: What are the principal competing solutions? How is your solution better?
MN: All the major EDA companies [Cadence, Mentor and Synopsys] have products in the assertion-based verification space. But, they have had limited success in this market. What we have done is to develop a product that can be easily used. Customers don’t have to learn PSL to use Verify. Once RTL designers begin to use automatic assertions they start to see the power of ABV, and can springboard into learning assertion-based languages like OVL or PSL.
CG: Do you have any customers for this solution?
MN: We are currently engaged with more than five partners. The reaction has been positive, and customers are enthused by the prospect of exploiting the power of ABV and reducing the high risk associated with functional bugs in their designs.
CG: What geographical regions are you targeting to market your solution?
MN: Today, a large number of semiconductor companies have development efforts in India. Therefore, many of our customers will be located in India, in addition to the USA, Europe and Japan. We see our strong presence in India as a strategic advantage.
CG: What are your main challenges in securing market acceptance of this solution?
MN: This is an emerging market, and the rate of adoption is going to be critical. Since previous solutions in this space have had limited success, there may be some skepticism about how this technology can be used to solve real problems.
CG: What is the two-year road map for this solution?
MN: The roadmap is to continue down the path of automatic assertions so that greater sophistication and capability is incorporated into the product. We will also look at higher performance and higher capacity, both of which will be needed as designs move to smaller geometries. We will continue to support existing assertion-based languages such as PSL and SVA.
Acronyms used:
EDA: Electronic Design Automation
ABV: Assertion Based Verification
PSL: Property Specification Language
OVL: Open Verification Library
SVA: System Verilog Assertions
www.atrenta.com
02 May 05
SiNett offers secure networking platform to OEMs
Partners with SafeNet to bundle security software, reference design
by Chitra Giridhar
Bangalore-based SiNett Corp. is collaborating with SafeNet Inc., a developer of security products and solutions, to create a reference platform for secure, enterprise-class networking products that will integrate wireless and wired access. The companies will combine SiNett's OneEdge, a purpose-built switch processor for unified wireless and wired enterprise networks, with SafeNet's QuickSec 3.0, a network security software solution.
Network equipment manufacturers can use the reference platform to build highly secure wireless LAN and Unified Access (UA) switches, and wireless LAN appliances. SafeNet's QuickSec 3.0 is a full-featured SDK for OEMs that includes IPSec VPN with IKEv2 authentication. A demo version of SafeNet's QuickSec will be included on SiNett's OneEdge-based OneRunner platform.
“This combined platform provides a compelling solution for our network OEM customers to efficiently build state-of-the-art secure network infrastructure gear with full support for wired and wireless capabilities,” comments Henk Pruim, vice president and general manager of SafeNet’s OEM/Networking Business Unit. “SafeNet's security software complements the VPN tunnel processing, access control, firewall and other security features included in our OneEdge devices,“ concurs Shrikant Sathe, co-founder of SiNett.
www.sinett.com
www.safenet-inc.com
Cadence Steps Up India Operations
by Chitra Giridhar
Cadence Design Systems (India) has disclosed plans to augment its staff from 700 to over 1,000 in the next few months. Speaking on the sidelines of an event to launch the Cadence RF Design Methodology Kit in Bangalore, Himanshu Singh, Executive Director for India and SAARC said some of this expansion is been driven by the growth in the Indian customers using Cadence tools. Cadence has two design and development centers in India, with its Noida (near Delhi) facility being the largest outside of the US.
It is estimated that more than 150 companies in the country are actively using a variety of Cadence tools. The software is also widely used in education sector, with many universities incorporating it into their engineering curriculum. To promote the use of EDA amongst the student community, the company has announced an EDA design contest for India and the SAARC region. According to Cadence, the contest will provide young designers an opportunity to showcase their best analog mixed signal/digital design projects to be judged by a panel of eminent experts from the industry.
www.cadence.com
18 November 2005
Motorola to expand presence in India, plans to assemble handsets in India
Chitra Giridhar
Motorola’s C115 handsets will now have a "Made in India" label said the company officials. "India is all about opportunity -- and today's announcements make it clear that Motorola is here to be a major player," said Allen Burnes, corporate vice president for the High Growth Markets operation within Motorola's Mobile Devices business.
"We're doing our part to leverage and create opportunities -- both for India and for Motorola. From our higher-end 'must haves' such as the new Motorola L6 candy bar and our best-selling RAZR clamshell, to our hugely popular C115, Motorola is helping connect the unconnected. This creates new and exciting opportunities -- and the potential for many new firsts -- for India's consumers."
The company expects the first Motorola C115 handsets assembled in India will be available by mid-December this year. Assembly in India is the first step in a multi-phase manufacturing strategy being deployed by Motorola in India.
The company also announced that it has selected India as the first market to launch its new ultra-sleek Motorola L6 mobile handset.
www.motorola.com
16 November 05
Tensilica enters design centre agreement with Tata Elxsi
by Chitra Giridhar
Tensilica, Inc., supplier of configurable and extensible microprocessor cores, has entered into an agreement with Bangalore-based Tata Elxsi Ltd., an embedded product design services company.
Based on the agreement, Tata Elxsi will become a recommended design center for Tensilica and Tata Elxsi's engineers will be fully trained on Tensilica's Xtensa(R) processor design technology.
"Having met Tensilica's high standards for an authorized design center, Tata Elxsi will now play a significant role in ensuring the broad and rapid proliferation of Xtensa cores in embedded applications," said Larry Przywara, director of strategic alliances for Tensilica.
As part of the "Tensilica Xtensions Network," design center members have been authorized to assist Xtensa licensees with the configuration, implementation and evaluation of system-on-chip (SoC) designs.
"The partnership reflects our intent to support product development services with technologies that enable significant performance benefits and faster time-to-market across various verticals," stated Mr. Madhukar Dev, CEO, Tata Elxsi.
The Xtensa configurable and extensible microprocessor architecture provides an integrated hardware and software development environment with thousands of configuration options and an unlimited range of customer-specific extensions. The environment enables designers to carefully tune the processor for their particular application.
www.tensilica.com
www.tataelxsi.com
12 November 05
Wipro’s Chairman receives IEE’s Faraday Award
by Chitra Giridhar
Azim Premji, Chairman of Wipro Ltd, was awarded the Faraday Medal by the Institution of Electrical Engineers (IEE)--the largest professional engineering society in Europe. He is the first Indian to receive this prestigious award.
The medal was awarded to him in recognition of his outstanding business leadership and contributions to elementary education in India. Sir Robin Saxby, Chairman of the UK-based ARM Technologies, a recipient of this award in 2002, presented the medal to Premji.
"The medal is actually a recognition of the untiring contribution made by the software engineers at Wipro and the Indian software community in general towards global technology," Premji said in his acceptance speech.
The Faraday Medal is a bronze medal established in 1922, and is awarded not more than once a year, either for notable scientific or industrial achievement in electrical engineering or for conspicuous service rendered to the advancement of electrical science, without restriction as regards nationality, country of residence or membership of the IEE.
Previous recipients of the Faraday Medal include Oliver Heaviside, the first person to receive the medal in 1922; Professor C.K. Kao, the “father” of fibre optic communications in 1989; and Professor P.M. Grant in recognition of his outstanding work on signal processing in 2004.
www.wipro.com
07 November 05
Synplicity to expand Bangalore centre
by Chitra Giridhar
US-based Synplicity, supplier of software for the design and verification of semiconductors, has expressed interest in increasing the scope of work and personnel at its R&D center in Bangalore. Bangalore centre does both development as well as support work. Recently, the five-year old development center has moved to take on autonomous development projects for the company.
Gary Meyers, president and CEO of Synplicity said that the company is doing more development in India. He said that nearly one-fifth of the company's overall R&D team was located in India, making Bangalore centre the second largest. "We have 40 employees at present, and we plan to increase this to 60 by the end of next year."
Synplicity provides tools for electronic design automation (EDA) designers who work on Field Programmable Gate Array (FPGA) synthesis, structured/platform ASIC synthesis and cell-based ASIC products. The company has done custom product development through joint R&D efforts for Altera and Xilinx to provide them exclusive tools.
The company's customer base spans organizations like Cisco Systems, HP, nVIDIA, Texas Instruments, Lockheed Martin, ST Microelectronics and Alcatel. Synplicity's competitors include Mentor Graphics and Synopsys.
www.synplicity.com
07 November 05
Indian government pursues Fab City project
by Chitra Giridhar
The Indian government is planning to build a semiconductor fabrication facility. The central government is surveying regional governments about water and electric facilities, and the concessions they could extend for the proposed project. The project is being supported by Minister for Communications and Information Technology Dayanidhi Maran, who is reportedly keen on having at least one major fabrication facility in the country. The blue print for the fab city will be ready in December.
“We are looking for about 1,500 acres of land for the project, of which 200 acres will be for the foundry and fab facility," says Madhavan Nambiar, Additional Secretary, Ministry of Information and Communication Technology. "A fab plant in India is the need of the hour," said India Semiconductor Association, Vice-Chairman, Anand AnandKumar.
The government is also contacting Taiwan’s Industrial Technology Research Institute (ITRI) to learn about promoting hardware growth in India. “An Indian team will visit ITRI in January,” Nambiar said.
www.isaonline.org
29 October 05
Huge potential and opportunity for semiconductor start-ups in India
by Chitra Giridhar
Availability of quality talent, thriving and collaborative ecosystem, key market drivers (healthy domestic and global market), labor costs are the factors conducive for an environment that fosters start-ups. This was the message at the conference, “Accelerating Technology Incubation in Semiconductor Space”, organized by the India Semiconductor Association (ISA).
S Uma Mahesh, ISA, said, “Semiconductor funding is different from funding a software-based start-up. Incubators need to play the role of a guide right through the initial stages. Incubation need not only be for the person starting a new company, it can also be for an established business with a great technology idea.”
“India Semiconductor Industry has a potential to grow to $40 billion by 2007. The industry can have a huge impact on the GDP of the country,” says Dr Anand Anandkumar, Vice Chairman, ISA. “I hope to see more entrepreneurs approaching the ISA and STPI for help in setting up businesses,” says Poornima Shenoy, President, ISA.
www.isaonline.org
12 October 05
ARM to increase headcount in India
by Chitra Giridhar
U.K.-based ARM is planning to expand its development centre and increase headcount in India. “We intend to do a lot more design activity in India,” said Sir Robin Saxby, Chairman, ARM Embedded Technologies Pvt. Ltd. The company currently has 120 team members in the country, and about 25 contractors according to Saxby. Four Indian companies, Wipro Ltd, HCL Technologies, Mindtree Consulting and Sasken Communications run ARM-approved design centers.
“We have grown ahead of our plans for the country in technology and commercial terms and we only expect to grow here,” said Saxby. He also commented on India’s advantage over China in the area of product patents--which is being driven by the nation’s growing market and design strengths.
www.arm.com
05 October 05
Simulation tools increase designer productivity
by Chitra Giridhar
Model-based design (MBD) is widely used by electronics, semiconductor and wireless industries to design complicated control systems in aerospace, automotive and industrial applications. It enables designers to mathematically and visually model the expected behavior of a product, design software, and simulate its behavior. Not surprisingly, MBD has become well entrenched in India.
According to Mathworks, a US-based company that makes tools for simulation and model-based design, there are more than 5,000 active users of its Matlab and Simulink tools in India. These users include GE India Technology Center, HAL (Hindustan Aeronautics), Tata Motors, TCS, Wipro Technologies, Aeronautical Development Agency (ADA), and IIT Delhi.
Arif Ali Saiyed, Software Engineer, Honeywell Technology Solution Lab, says, “Honeywell uses Matlab Simulink for designing lighting control systems. This software eliminates many manual processes--saving time and development costs.” He feels that no other competing products offer these benefits.
Ritwik Majumder, Senior System Engineer, Siemens Information Systems Ltd. concurs that MBD tools reduce cost and effort by enabling designers visualize results and tune designs. Siemens designs automotive engine management systems and power trains. The company uses Mathlab Simulink models for the control algorithms.
However, Arif feels that more features could be added in the Mathlab. He says that the state-flow coder needs to be enhanced to support Honeywell’s business needs--and product support can be enhanced.
www.mathworks.com
www.htc.honeywell.com
www.siemens.com
04 October 05
Midas selects Infineon chips for fixed wireless product
Targets telcos with broadband VOIP access device
by Chitra Giridhar
Chennai-based Midas Communication Technologies, provider of network access solutions, has selected Infineon Technology’s customized system-on-chip (SoC) solution, INCA-IP, for its broadband corDECT-based fixed wireless access indoor unit. The INCA-IP is a cost-optimized solution for VoIP terminals that offers advanced features such as voice packet prioritization, integrated voice codecs with conferencing functionality, echo-cancellation, and an integrated 3 port Ethernet switch.
“When selecting a SoC solution for the controller in the corDECT indoor unit we looked for one that would facilitate complete host controller functionality, with the smallest footprint and power consumption,” said Rene Abraham, CTO, Midas. The company’s new products based on this SoC will support data rates up to 256 Kbps--more than two and a half times higher than competing platforms.
Midas' current activities in access technologies include "BroadbandcorDECT" a fixed wireless access solution, to cater to the 'last-mile' requirements of wireless service providers, and "Broadband DIAS", an integrated fiber in local loop platform for telephony and broadband services.
www.midascomm.com
www.infineon.com
04 October 05
Indian tool company partners to bring new software tools
by Chitra Giridhar
Bangalore-based scientific and engineering software products and solutions provider, Cranes software has tied-up with Mapusoft Technologies (MT), to bring OSChanger and OS Abstractor software tools to the Indian embedded industry.
While OS Changer allows developers to easily port existing code base to another RTOS and continue code development using the familiar API (application programming interface), OS Abstractor allows developers to write code that can be easily adapted to multiple RTOS’s. OSChanger reduces testing efforts and related risks, and ensures a smooth and successful RTOS transition.
By providing wrapper-less RTOS abstraction APIs, Unix-style device I/O APIs, and a set of core ANSI APIs, OSChanger provides an off-the-shelf RTOS integration solution that enables customers to re-use existing code base and port open source and/or other solutions to theirs easily., all of which are accomplished using a familiar API to get the job done much faster.
OS Abstractor is available for Linux, iTRON, Nucleus PLUS(r), ThreadX(r), Precise/MQX(tm) and other RTOS’s OS Abstractor consists of a set of RTOS-equivalent functions and Unix-style device I/O functions that are highly optimized for specific RTOS’s. Many of the kernel-equivalent RTOS functions are directly mapped to the underlying API and data structures, allowing the translations to occur during compile time, so that run-time performance can be kept intact. The interface to the underlying target RTOS is isolated in a single module to allow easy extension of support to a proprietary or preferred commercial RTOS.
www.cranessoftware.com
www.mapusoft.com
04 October 2005
Mistral announces next gen IP media processing platforms
by Chitra Giridhar
Indian embedded software and hardware development firm, Mistral Solutions, has announced IP media processing platforms, CG 6565 and CG 6060, to deliver increased IP packet processing capability for IVR, fax, conferencing, VoIP and 3G video. The CG 6565 is a high-performance board designed for processing-intensive applications like IP media servers, VoIP gateways, video gateways and media servers. The CG 6060 is a medium-powered board appropriate for a broad range of applications, from high-density trunking with up to 16 E1/T1s, to IVR, fax, conferencing, and MRCP speech. Both the CG 6565 and CG 6060 are available in PCI and compact PCI format.
This new technology is supported by NMS’ development environment, natural access and support MRCP speech servers from all the popular speech vendors through NMS’ Uni
versal Speech Access API (application programming interface). NMS Communications is a mobile application and infrastructure solutions provider.
www.mistralsoftware.com
11 July 2005
eInfoChips targets burgeoning demand for DSPs
Enhances focus on TI’s platforms, adds design staff
by Chitra Giridhar
eInfochips, a chip and systems design services firm with operations in Ahmedabad and Pune, India is collaborating with Texas Instruments (TI) to develop DSP-based reference applications like IP set-top boxes and digital video recorders for OEM designs.
To tap the growing demand for DSP-based designs, eInfochips is ramping up the strength of its engineering team from the current 50 to more than 100 in the next few months. Simultaneously, the company plans to expand its reach in Europe and Asia-Pacific to service TI customers.
The company has already developed several reference designs on TI C6x and DM64x platform, including a KVM/IP (Keyboard, Video, Mouse over IP) for remote server management, a rapid development platform for multimedia applications like DVRs and video conferencing systems, and a networked video application.
eInfochips also offers system integration services to customers developing products on the TI TMS320C6000 DSP platforms, and the TMS320DM64x DSP-based digital media processors. These services include algorithm design and development, selection of DSP processor best suited for the application, processor specific optimization of software, porting and preparing board support packages for RTOS on DSP, and developing board level systems and firmware solutions on DSP.
www.einfochips.com
www.ti.com
05 July 05
Open-Silicon sets up first Design Center Unit in Bangalore
by Chitra Giridhar
Open-Silicon Inc, a fables ASIC company has set up their first design centre unit (DCU) in Bangalore. Built with a world-class silicon engineering and execution capability,Open-Silicon has taped-out 15 chips in the first year of operation. A DCU uses dynamic staffing of technology experts who are specialized in particular silicon-engineering areas. This ensures their customers get a repeatable, predictable and reliable design process for custom ASIC development.
Dr. Naveed Sherwani, President & CEO, Open-Silicon said, "India has been, and continues to be, a very critical part of our growth strategy. The high quality of engineering talent has allowed us to build a multi-function site capable of managing all aspects of silicon engineering. This, combined with the support we have received from the government and industry will allow us to continue to scale to greater heights."
Co-founder and VP Engineering, Dr. Satya Gupta said, "The quality of experienced engineering, university programs that ensure continuous growth of VLSI talent, and local support from ASIC partners for chip design activity make India the ideal place for our silicon engineering efforts. We hope to add our next DCU, double our present work force in 2006 and tape-out 20-25 chips."
www.open-silicon.com
05 July 05
Tessolve sets up product test facility in Bangalore
First to offer services in Asia-Pac region
by Chitra Giridhar
Tessolve Inc. is setting up a facility to provide product engineering (RF, Digital & Mixed Signal) services to global and local customers. This test lab is located in Bangalore’s Semicon Park, a one-stop post-design and post-fab, service facility for semiconductor companies.
The $10 million engineering and testing facility is spread over 50,000 sq. ft. and has an extensive array of advanced testing equipment. Currently the Indian operations employs more than 50 testing professionals with experience in wafer sort, final test development (RF, Digital and Mixed signal) and device characterization. P Raja Manickam, Founder & CEO, Tessolve, says, “This facility, which is equipped to provide world class test development, failure analysis and reliability testing will allow semiconductor companies to go beyond GDS II, for the first time in India.”
According to V Veerappan, vice-president of operations at Tessolve, the company will serve organizations like Texas Instruments, STM, Agere, Broadcom, Insilica, Sitar, SCL and Beceem Communications. Speaking at the inauguration of the facility, Johny Mathew, CEO of Semicon Park said, “The Indian semiconductor industry has been primarily in the design and related services. However, being limited only to being a design services hub has a strategic disadvantage--as it constrains the total value that we can provide. India needs to offer a much more comprehensive ecosystem--which is being realized now.” Concurrs Rajendra Kumar Khare, Chairman of Indian Semiconductor Association (ISA), “The setting up of full-fledged testing facility marks a move towards creating a complete ecosystem for the Indian semiconductor industry.”
www.tessolve.com
www.isaonline.org
30 June 05
Philips expands its India design center
Focus on next generation consumer chips, reusable IP blocks
by Chitra Giridhar
Philips Semiconductors has announced that its Bangalore design center would be working on the next generation consumer platform chip design. Chief Technology Officer Rene Penning de Vries said, "Our center is now fully staffed, and we are embarking on designs in 65 and 90nm. The next generation consumer platform chip will enable new applications such as HD motion based enhancements and 3D TV. It will be the biggest chip we have ever designed in this company and will consist of multiple MIPS and Trimedia (DSP) processors.” The Trimedia processor is a Philips proprietary DSP based on VLIW architecture and allows for video signal processing.
Penning de Vries confirmed that the development of the chip will involve collaborative efforts across multiple sites in Europe and US. “Our Bangalore team will be integrating the whole chip. We will also be working with Philips Research in Bangalore and the Netherlands.”
In addition to working on the new chip, the Bangalore center will also focus on reusable IP. “Our team here will become responsible for a large part of our reuse portfolio. We are enhancing our IP development, and expanding our work in the areas of connectivity peripherals. Our competencies in the reuse IP portfolio include connectivity blocks, wired and wireless, intra and inter chip; SoC, peripherals and drivers. These are being leveraged to provide SoC integrators with ready to use subsystems, which can be easily plugged to build complex SoCs,” Penning de Vries said.
Philips Semiconductor has more than 500 people and working on latest technologies in SoC and embedded software. To support its development efforts, the company plans to hire more many engineers over the next three years.
www.semiconductors.philips.com
24 June 05
Indian startup provides offshore engineering support services
Targets semiconductor, instrumentation and medical electronics sectors
by Chitra Giridhar
Vignani Technologies, a product engineering services company, has commenced operations in Bangalore. Targeting the international semiconductor, instrumentation and medical electronics industries, Vignani offers engineering support services like PCB test and design, modeling, engineering change implementation, embedded solutions and value engineering services.
Explains Tom Rohrs, Chairman, Vignani Technologies, “India is emerging as an important destination for Engineering services. Large multinationals continually allocate scarce engineering manpower to their next generation products, leaving critical revenue producing products under-resourced. Vignani will step in and fill this void.” Funded by a combination of angel and venture capital, Vignani is aiming to hire 750 to 1000 engineers over the next three years. The facility in Bangalore will focus on delivering the services to customers in US, Europe and Japan.
www.vignani.com
16 June 2005
einfochips to double headcount
Plans to tap markets in Europe and Asia
by Chitra Giridhar
eInfochips, a chip & systems design services firm based in Santa Clara, USA and Ahmedabad, India, plans to double the headcount at its research and development centers this year and tap new markets. The company plans to increase the headcount at its design centers from the current strength of 270 engineers to over 550 engineers. eInfochips has a state-of-the-art 40000 sq. ft. design center employing over 250 design engineers in Ahmedabad.
“We plan to open our first office in Europe either in UK or Germany, while for Asia-Pacific region, Japan is under active consideration,” says Pratul Shroff, President & CEO, eInfochips.
“The demand for technology services is large and we see ourselves growing rapidly. The market potential for outsourced engineering services is estimated to lie between $ 7 to $12 billion and around 20% of the value is being outsourced to third party vendors in countries like India, Taiwan and China which highlights significant untapped potential. We will recruit a large number of engineers this year and offer them an opportunity to work on cutting edge technology like GPS navigation, digital MP3 players, video-on-demand, UWB (wireless) and SAN (storage area networking),’’ adds Shroff.
“eInfochips has been founded with a singular vision: to build an enduring, world-class technology services organization to serve customers globally. People are the key in realizing this vision. We are strongly focused on helping each individual maximize his potential,” adds Shroff.
eInfochips has specialization in design and verification of Application Specific Integrated Chips (ASIC) and provides embedded systems solutions, application software and IP cores to world’s best-known technology companies such as Samsung, Texas Instruments, Cadence, Rambus, Qlogic, Tensilica, Cypress Semiconductor, Agere, Navionics, Sun Microsystems and NetEffect.
eInfochips has recently opened up two more sales offices in US in Boston and Austin, and one sales office in India at Banglore. Last year it set up a new development and design facility in Pune. The Pune Center is executing offshore projects for global blue chip technology companies like QLogic and Tensilica.
eInfochips has proven competencies in the complete product development life cycle, right from Hardware Design, Firmware Development, Multimedia Codecs, Communication stacks, and application development. ‘DSPKarma™’ is the suite of DSP Services that includes DSP Hardware, Software and System Integration. eInfochips has also recently introduced ‘ChipMaestro’- the industry’s first suite of solutions and services, as a single source of offshore expertise in the design, development and verification of SoCs, ASICs or FPGAs for the communications and computer peripheral markets.
www.einfochips.com
06 June 05
SiNett simplifies integration of wired, wireless LANs
Reference platform for unified networks bundles management software for rapid prototyping
by Chitra Giridhar
SiNett Corp., a developer of silicon for networking apps is partnering with NextHop Technologies Inc., network software solutions provider to support the design of enterprise-class integrated wireless and wired network access products. According to Shrikant Sathe, co-founder and vice president of marketing at SiNett, “Our technology coupled with NextHop's WLAN controller software will provide equipment manufacturers with a flexible solution for building and managing unified wireless and wired network infrastructures.”
The partnership envisages tight coupling of SiNett's switch processor and NextHop's wireless LAN controller software (WCS) to meet enterprise requirements for L2/L3 switching and wireless LAN (WLAN) management. These include the provisioning of seamless mobility, enhanced security, quality of service (QoS) and advanced traffic management. OEMs and ODMs using the solution can deploy the switch process and controller software combination in equipment designed for any layer in the network.
A demo version of NextHop's software will be included with SiNett's OneEdge-based OneRunner platform, a reference design for developing secure WLAN and unified access (UA) switches and WLAN appliances. OneRunner is designed to support different access point architectures such as ultra-thin and thin access points. SiNett’s SN5024 UA switch processor incorporates 24 Fast Ethernet (FE) and 4 Gigabit Ethernet (GE) interfaces, and can be used in fixed configuration or stackable Unified Access switches. The NextHop demo software provides advanced security, authentication, mobility, QoS and centralized management for WLAN (802.11) access points.
www.sinett.com
www.nexthop.com
03 June 05
HCL, NEC form joint venture company
New entity to deliver offshore-based services to Japan clients
by Chitra Giridhar
NEC Corp. has entered into a joint venture with India-based HCL Technologies Limited (HCL) for offshore software engineering solutions in embedded software, hardware design, network & security, R&D, high performance computing, and mobile technology to NEC, its subsidiaries and their clients, in Japan and globally. NEC Corp. and its subsidiary, NEC System Technologies Ltd, will have a 51% stake in the joint venture, while remaining will be held by HCL. The new company is expected to achieve revenues of about US $25 million in three years.
The joint venture will be based out of Noida, India. HCL will provide the CEO and CTO, along with some key technical people to initiate the JV. This alliance is a part of NEC's strategic intent to harness Indian IT prowess and leverage its IT eco-system advantages to provide greater value of IT products and services to its subsidiaries and their clients globally. Hiroshi Oka, Associate Senior Vice President, NEC System Technologies Ltd. said, "I have a lot of expectations from the JV and HCL in areas such as embedded software, network and security products, hardware design and related tools."
www.hcltech.com
www.nec.com
20 May 05
Toolkit solves post-layout data organization
Interfaces to existing tools, and speeds development of custom solutions
by Chitra Giridhar
Bangalore-based SoftJin Infotech Pvt. Ltd. has developed an EDA toolkit that addresses the challenges of geometric data-organization at the post layout stage of the sub-90 nm IC manufacturing process. According to the company, Nirmaan, is a performance tuned and customized toolkit that obviates the need for EDA tool developers to develop their own code for geometrical operations. Nachiket Urdhwareshe, CEO, Softjin says, “Our goal is to support the development of customized DFM/DFY tools with our building blocks and services".
Nirmaan provides APIs for post-layout EDA tool developers to enable them integrate the toolkit into their own solutions. Nirmaan stores and represents geometric data in multiple levels of organizations (including structural, spatial and basic geometry levels), and allows mixing and matching of different types of organizations at different levels. The flexibility of data organization makes the toolkit highly efficient for performing the geometrical operations required in post-layout tools. The data is stored in compressed form and is decompressed on-the-fly. API’s are available for the tool developers to plug-in customized data models.
The built-in geometrical operations in Nirmaan include boolean, sizing, islanding, tiling/binning and window querying. These operations work on the in-memory data organization, and can be performed at polygon, cell, island, window, layer, block and full-chip levels. To boost performance, the toolkit’s data-organization and operations support multi-threading and distributed computing. The product interfaces with other applications through standard industry layout data formats and databases like GDSII, OASIS, LEF/DEF and OpenAccess.
Nirmaan can be used to accelerate product development for companies developing new post layout tools. Also, companies with existing post layout EDA products can adopt the product to improve the performance and scalability of their current solutions. The toolkit is licensed as object code, and can be included and sold as part of post-layout tools. Licenses start at $150,000. Nirmaan is currently available to select beta sites, and will be in production release in Q3-2005. The toolkit will be demonstrated at the Design Automation Conference in Anaheim, June 13-16 [SoftJin booth # 1956].
www.softjin.com
17 May 05
“Assertion-based design verification is a pre-emptive approach”
by Chitra Giridhar
San Jose-based Atrenta Inc. has developed a chip verification solution, 1Team:Verify, that enables IC designers detect and prevent hard-to-find bugs earlier in design process. The solution can detect many "corner-case" bugs that traditional simulation-based verification methods can miss. Examples include errors involving clock domain crossings (CDCs), finite state machines (FSMs), handshake mechanisms and bus structures. Verify can generate and validate a large number of assertions (over 10,000 assertions for a 500,000-gate design on average) without any user intervention.
Verify allows RTL designers to carry out many ABV checks themselves, thus saving time and cost. In addition to its fully automatic checking, Verify also allows more experienced users to write their own assertions using other assertion languages. Verify supports the open verification library (OVL)--an Accellera-standard library of 31 predefined assertions from which users can choose. Extensions to OVL are also supported for users who want to define new assertions using the OVL paradigm. PSL (Property Description Language) and SVA (System Verilog Assertions) are also available as Verify options.
Mani Narayan, Product Marketing Director for Atrenta talks to Chitra Giridhar about Verify.
CG: How long did it take you to develop the Verify solution?
MN: Verify is built on some of the key technologies that form the foundation of Atrenta’s SpyGlass product [introduced in January 2001]. Additional technology was developed to provide in-depth functional verification, and seek out hard to find functional problems. The new technology for Verify took more than 2 years to develop, and the product represents more than 40,000 man hours of work. More than 90% of the development was done at our Noida, India facility.
CG: What were the main challenges you encountered in developing the solution?
MN: First a historical perspective. Formal verification technology has been around for 10 years and all assertion based verification products developed using this technology have been difficult for RTL designers to use. The need to learn a language like PSL and getting familiar with the formal terminology have all been barriers to adoption. The process of understanding user needs and translating them into features that could be mapped into technologies was one of the key challenges.
CG: What are the principal competing solutions? How is your solution better?
MN: All the major EDA companies [Cadence, Mentor and Synopsys] have products in the assertion-based verification space. But, they have had limited success in this market. What we have done is to develop a product that can be easily used. Customers don’t have to learn PSL to use Verify. Once RTL designers begin to use automatic assertions they start to see the power of ABV, and can springboard into learning assertion-based languages like OVL or PSL.
CG: Do you have any customers for this solution?
MN: We are currently engaged with more than five partners. The reaction has been positive, and customers are enthused by the prospect of exploiting the power of ABV and reducing the high risk associated with functional bugs in their designs.
CG: What geographical regions are you targeting to market your solution?
MN: Today, a large number of semiconductor companies have development efforts in India. Therefore, many of our customers will be located in India, in addition to the USA, Europe and Japan. We see our strong presence in India as a strategic advantage.
CG: What are your main challenges in securing market acceptance of this solution?
MN: This is an emerging market, and the rate of adoption is going to be critical. Since previous solutions in this space have had limited success, there may be some skepticism about how this technology can be used to solve real problems.
CG: What is the two-year road map for this solution?
MN: The roadmap is to continue down the path of automatic assertions so that greater sophistication and capability is incorporated into the product. We will also look at higher performance and higher capacity, both of which will be needed as designs move to smaller geometries. We will continue to support existing assertion-based languages such as PSL and SVA.
Acronyms used:
EDA: Electronic Design Automation
ABV: Assertion Based Verification
PSL: Property Specification Language
OVL: Open Verification Library
SVA: System Verilog Assertions
www.atrenta.com
02 May 05
SiNett offers secure networking platform to OEMs
Partners with SafeNet to bundle security software, reference design
by Chitra Giridhar
Bangalore-based SiNett Corp. is collaborating with SafeNet Inc., a developer of security products and solutions, to create a reference platform for secure, enterprise-class networking products that will integrate wireless and wired access. The companies will combine SiNett's OneEdge, a purpose-built switch processor for unified wireless and wired enterprise networks, with SafeNet's QuickSec 3.0, a network security software solution.
Network equipment manufacturers can use the reference platform to build highly secure wireless LAN and Unified Access (UA) switches, and wireless LAN appliances. SafeNet's QuickSec 3.0 is a full-featured SDK for OEMs that includes IPSec VPN with IKEv2 authentication. A demo version of SafeNet's QuickSec will be included on SiNett's OneEdge-based OneRunner platform.
“This combined platform provides a compelling solution for our network OEM customers to efficiently build state-of-the-art secure network infrastructure gear with full support for wired and wireless capabilities,” comments Henk Pruim, vice president and general manager of SafeNet’s OEM/Networking Business Unit. “SafeNet's security software complements the VPN tunnel processing, access control, firewall and other security features included in our OneEdge devices,“ concurs Shrikant Sathe, co-founder of SiNett.
www.sinett.com
www.safenet-inc.com
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